Manufacturing method of semiconductor structure

ABSTRACT

Present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate, forming a first III-V compound layer over the substrate, forming a first passivation layer over the first III-V compound layer, forming a first opening from a top surface of the first passivation layer to the first III-V compound layer, each opening having a stair-shaped sidewall at the first passivation layer, depositing a metal layer over the first passivation layer and in the first opening, the metal layer having a second opening above the corresponding first opening, and removing a portion of the metal layer to form a source electrode and a drain electrode.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of prior-filed U.S. non-provisional application Ser. No. 15/062,972 filed Mar. 7, 2016 and Ser. No. 16/199,563 filed Nov. 26, 2018 under 35 U.S.C. 120.

FIELD

The present disclosure relates generally to a semiconductor structure and a method of manufacturing a semiconductor structure.

BACKGROUND

In semiconductor technology, due to their characteristics, Group III-Group V (or III-V) semiconductor compounds are used to form various integrated circuit devices, such as high power field-effect transistors, high frequency transistors, or high electron mobility transistors (HEMTs). A HEMT is a field effect transistor incorporating a junction between two materials with different band gaps (i.e., a heterojunction) as the channel instead of a doped region, as is generally the case for metal oxide semiconductor field effect transistors (MOSFETs). In contrast with MOSFETs, HEMTs have a number of attractive properties including high electron mobility, the ability to transmit signals at high frequencies, etc.

From an application point of view, enhancement-mode (E-mode) HEMTs have many advantages. E-mode HEMTs allow elimination of negative-polarity voltage supply, and, therefore, reduction of the circuit complexity and cost. Despite the attractive properties noted above, a number of challenges exist in connection with developing III-V semiconductor compound-based devices. Various techniques directed at configurations and materials of these III-V semiconductor compounds have been implemented to try and further improve transistor device performance.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1A is a cross-sectional view of a semiconductor structure in accordance with some embodiments of the present disclosure.

FIG. 1B illustrates an enlarged view of the semiconductor structure in FIG. 1A, taken along the dotted rectangle A in accordance with some embodiments of the present disclosure.

FIGS. 2A-2H are a series of cross-sectional views illustrating processing steps to fabricate the semiconductor structure, in accordance with some embodiments of the present disclosure.

FIGS. 3A-3F are a series of cross-sectional views illustrating processing steps to fabricate the semiconductor structure, in accordance with some embodiments of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The making and using of the embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

FIG. 1A is a cross-sectional view of a semiconductor structure 1 according to one or more embodiments of the present disclosure. In some embodiments, the semiconductor structure 1 may be a high electron mobility transistor (HEMT). The semiconductor structure 1 includes a substrate 10, a first III-V compound layer 13, a second III-V compound layer 11, isolation regions 12, a source region 14, a drain region 15, a gate region, a first passivation layer 17, a second passivation layer 18 and a buffer layer 19.

In some embodiments, the substrate 10 includes a silicon carbide (SiC) substrate, sapphire substrate or a silicon substrate. The semiconductor structure 10 also includes a heterojunction formed between two different semiconductor material layers, such as material layers with different band gaps. For example, the semiconductor structure 10 includes a non-doped narrow-band gap channel layer and a wide-band gap n-type donor-supply layer.

The buffer layer 19 is on the substrate 10. The buffer layer 19 acts as the buffer and/or the transition layer for the subsequently formed overlying layers. The buffer layer 19 may be epitaxially grown using Metal Organic Vapor Phase Epitaxy (MOVPE). The buffer layer 19 may function as an interface to reduce lattice mismatch between substrate 10 and the second III-V compound layer 11. In some embodiments, the buffer layer 19 includes an aluminum nitride (AlN) layer having a thickness in a range between about 10 nanometers (nm) and about 300 nm. The buffer layer 19 may include a single layer or a plurality of layers. For example, the buffer layer 19 may include a low-temperature AlN layer (not shown in the drawing) formed at a temperature between about 800° C. and about 1,200° C., and a high-temperature AlN layer (not shown in the drawing) formed at a temperature between about 1,000° C. and about 1,400° C.

The second III-V compound layer 11 is on the buffer layer 19. The second III-V compound layer 11 is a compound made from the III-V groups in the periodic table of elements. In some embodiments of the present example, the second III-V compound layer 11 includes a gallium nitride (GaN) layer. In some embodiments, the second III-V compound layer 11 includes a GaAs layer or InP layer. In some embodiments, the second III-V compound layer 11 may be epitaxially grown by using, for example, MOVPE, during which a gallium-containing precursor and a nitrogen-containing precursor are used. The gallium-containing precursor may include trimethylgallium (TMG), triethylgallium (TEG), or other suitable gallium-containing chemicals. The nitrogen-containing precursor may include ammonia (NH₃), tertiarybutylamine (TBAm), phenyl hydrazine, or other suitable chemicals.

The second III-V compound layer 11 is undoped. Alternatively, the second III-V compound layer 11 is unintentionally doped, such as lightly doped with n-type dopants due to a precursor used to form the second III-V compound layer 11. In some embodiments, the second III-V compound layer 11 has a thickness in a range from about 0.5 microns (μm) to about 10 μm.

The first III-V compound layer 13 is on the second III-V compound layer 11. The first III-V compound layer 13 is a compound made from the III-V groups in the periodic table of elements. The first III-V compound layer 13 and the second III-V compound layer 11 are different from each other in composition. In some embodiments of the present example, the first III-V compound layer 13 includes an aluminum gallium nitride (AlGaN) layer. In some embodiments, the first III-V compound layer 13 includes an AlGaAs layer or an AlInP layer.

The first III-V compound layer 13 is intentionally doped. In some embodiments, the first III-V compound layer 13 has a thickness in a range from about 5 nm to about 50 nm.

The source region 14 is on the first III-V compound layer 13. In some embodiments, the source region 14 includes Au and comprises Al, Ti, Ni, Au or Cu. The drain region 15 is on the first III-V compound layer 13 and spaced apart from the source region 14. In some embodiments, the drain region 15 includes Au and comprises Al, Ti, Ni, Au or Cu.

The gate region 16 is on the first III-V compound layer 13 and between the source region 14 and the drain region 15. The gate region 16 includes a conductive material layer configured for voltage bias. In some embodiments, the conductive material layer includes a refractory metal or its compounds, e.g., titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW) and tungsten (W). Alternatively, the conductive material layer includes nickel (Ni), gold (Au) or copper (Cu).

The isolation regions 12 are at both sides within the second III-V compound layer 11 and the first III-V compound layer 13. The isolation regions 12 isolate the HEMT in the semiconductor structure 1 from other devices in the substrate 10. In some embodiments, the isolation regions 12 include doped regions with species of oxygen or nitrogen.

The first passivation layer 17 is on the first III-V compound layer 13 and the isolation layers 12. The first passivation layer 17 surrounds a portion of the source region 14, the drain region 15 and the gate region 16. The first passivation layer 17 is configured to protect the underlying first III-V compound layer 13 from damage in the process having plasma. In some embodiments, the first passivation layer 17 has a thickness in a range between about 100 Å and about 5,000 Å. In some embodiments, the first passivation layer 17 includes silicon oxide and/or silicon nitride. When comprising silicon nitride, the first passivation layer 17 may be formed by performing a Low-Pressure Chemical Vapor Deposition (LPCVD) method (without plasma) using SiH₄ and NH₃ gases.

The second passivation layer 18 is on the first passivation layer 17 and covers the remaining portions of the source region 14 and the drain region 15 that are not covered by the first passivation layer 17. In some examples, the second passivation layer 18 comprises silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide or hafnium oxide.

In some embodiments, the semiconductor structure 1 may further include a protection layer (not shown in the drawing). The protection layer is disposed between the source region 14 and the second passivation layer 18 and between the drain region 15 and the second passivation layer 18. The protection layer covers the source region 14 and the drain region 15, and prevents the source region 14 and the drain region 15 from exposure during an annealing process in the formation of the isolation regions 12.

In the above described embodiments, the gate region 16, the source region 14 and the drain region 15 are configured as a transistor. When a voltage is applied to the gate stack, a device current of the transistor could be modulated.

FIG. 1B illustrates an enlarged view of the source region 14 of the semiconductor structure 1 of FIG. 1A, taken along the dotted rectangle A. As shown in FIG. 1B, the first III-V compound layer 13 has a concave portion in which the source region 14 is located. The first III-V compound layer 13 is a compound made from the III-V groups in the periodic table of elements. In some embodiments of the present example, the first III-V compound layer 13 includes an aluminum gallium nitride (AlGaN) layer. In some embodiments, the first III-V compound layer 13 includes an AlGaAs layer or an AlInP layer. The first III-V compound layer 13 is intentionally doped. In some embodiments, the first III-V compound layer 13 has a thickness in a range from about 5 nm to about 50 nm.

The first passivation layer 17 is located on the first III-V compound layer 13. The first passivation layer 17 has an opening. The sidewall of the opening has two stair-shaped portions 17 a. In some embodiments, the height h1 of the sidewall of the concave portion and the lower step of the stepped-shape portion 17 a is greater than the height h2 of the sidewall of the upper step of the stepped-shape portion 17 a. In some embodiments, the width w1 of the stepped-shape portion 17 a is in a range from about 0.03 μm to about 0.05 μm.

The first passivation layer 17 is configured to protect the underlying first III-V compound layer 13 from damage in plasma-related process. In some embodiments, the first passivation layer 17 has a thickness in a range between about 100 Å and about 5,000 Å. In some embodiments, the first passivation layer 17 includes silicon oxide and/or silicon nitride. When comprising silicon nitride, the first passivation layer 17 may be formed by performing a Low-Pressure Chemical Vapor Deposition (LPCVD) method (without plasma) using SiH₄ and NH₃ gases.

The source region 14 is located in a recess of the first passivation layer 17 and a recess of the first III-V compound layer 13. In some embodiments, the source region 14 includes Au, Al, Ti, Ni, Au or Cu.

The second passivation layer 18 is on the first passivation layer 17 and covers the portions of the source region 14 that are not covered by the first passivation layer 17. In some examples, the second passivation layer 18 comprises silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide or hafnium oxide.

As shown in FIG. 1A, the on resistance (Ron) of the semiconductor structure 1 is proportional to the distance Lgs between the source region 14 and the gate region 16, the width Lg of the gate region 16 and the distance Lgd between the drain region 15 and the gate region 16. The distance Lgs includes the overlaying portion of the source region 14 and the first passivation layer 17. Similarly, the distance Lgd includes the overlaying portion of the drain region 15 and the first passivation layer 17. According to the present disclosure, the length of overlaying portion is defined by the width w1 of the stepped-shape portion 17 a. In comparison with the existing semiconductor structure (in which the overlay length is about 0.2 μm), the semiconductor structure 1 shown in FIG. 1A has smaller overlaying length (in a range from about 0.03 μm to about 0.05 μm). Reducing the overlay length would reduce the length Lgs and Lgd, which would in turn reduce the on resistance of the semiconductor structure 1.

FIG. 2A to FIG. 2H are cross-sectional views of a CMOS-MEMS structure fabricated at various stages, in accordance with some embodiments of the present disclosure. Various figures have been simplified for a better understanding of the inventive concepts of the present disclosure.

Referring to FIG. 2A, a substrate 20 is provided. The substrate 20 includes a silicon carbide (SiC) substrate, sapphire substrate or a silicon substrate. The semiconductor structure 20 also includes a heterojunction formed between two different semiconductor material layers, such as material layers with different band gaps. For example, the semiconductor structure 20 includes a non-doped narrow-band gap channel layer and a wide-band gap n-type donor-supply layer.

The buffer layer 29 is formed on the substrate 20. The buffer layer 29 acts as the buffer and/or the transition layer for the subsequently formed overlying layers. The buffer layer 29 may be epitaxially grown using Metal Organic Vapor Phase Epitaxy (MOVPE). The buffer layer 29 may function as an interface to reduce lattice mismatch between substrate 20 and the subsequently formed III-V compound layer. In some embodiments, the buffer layer 29 includes an aluminum nitride (AlN) layer having a thickness in a range between about 10 nanometers (nm) and about 300 nm. The buffer layer 29 may include a single layer or a plurality of layers. For example, the buffer layer 29 may include a low-temperature AlN layer (not shown in the drawing) formed at a temperature between about 800° C. and about 1,200° C., and a high-temperature AlN layer (not shown in the drawing) formed at a temperature between about 1,000° C. and about 1,400° C.

The second III-V compound layer 21 is formed on the buffer layer 19. The second III-V compound layer 21 is a compound made from the III-V groups in the periodic table of elements. In some embodiments of the present example, the second III-V compound layer 21 includes a gallium nitride (GaN) layer. In some embodiments, the second III-V compound layer 21 includes a GaAs layer or InP layer. In some embodiments, the second III-V compound layer 21 may be epitaxially grown by using, for example, MOVPE, during which a gallium-containing precursor and a nitrogen-containing precursor are used. The gallium-containing precursor may include trimethylgallium (TMG), triethylgallium (TEG), or other suitable gallium-containing chemicals. The nitrogen-containing precursor may include ammonia (NH₃), tertiarybutylamine (TBAm), phenyl hydrazine, or other suitable chemicals.

The second III-V compound layer 21 is undoped. Alternatively, the second III-V compound layer 21 is unintentionally doped, such as lightly doped with n-type dopants due to a precursor used to form the second III-V compound layer 21. In some embodiments, the second III-V compound layer 21 has a thickness in a range from about 0.5 μm to about 10 μm.

The first III-V compound layer 23 is formed on the second III-V compound layer 21. The first III-V compound layer 23 is a compound made from the III-V groups in the periodic table of elements. The first III-V compound layer 23 and the second III-V compound layer 21 are different from each other in composition. In some embodiments of the present example, the first III-V compound layer 23 includes an aluminum gallium nitride (AlGaN) layer. In some embodiments, the first III-V compound layer 23 includes an AlGaAs layer or an AlInP layer. The first III-V compound layer 23 is intentionally doped. In some embodiments, the first III-V compound layer 23 has a thickness in a range from about 5 nm to about 50 nm. The first III-V compound layer 23 is epitaxially grown on the second III-V compound layer 21 by MOVPE using aluminum-containing precursor, gallium-containing precursor, and nitrogen-containing precursor. The aluminum-containing precursor includes trimethylaluminum (TMA), triethylaluminium (TEA), or other suitable chemical. The gallium-containing precursor includes TMG, TEG, or other suitable chemical. The nitrogen-containing precursor includes ammonia, TBAm, phenyl hydrazine, or other suitable chemical.

The isolation regions 22 are formed in the second III-V compound layer 21 and at both edges of the first III-V compound layer 23. In some embodiments, the isolation regions 22 are formed by an implantation process with species of oxygen or nitrogen.

The first passivation layer 27 is formed on the first III-V compound layer 23 and the isolation layers 22. In some embodiments, the first passivation layer 27 has a thickness in a range between about 100 Å and about 5,000 Å. In some embodiments, the first passivation layer 27 includes silicon oxide and/or silicon nitride. In some embodiments, the first passivation layer 27 is formed by performing a low pressure chemical vapor deposition (LPCVD) method without plasma using SiH₄ and NH₃ gases. An operation temperature is in a range of from about 650° C. to about 800° C. An operation pressure is in a range of about 0.1 Torr and about 1 Torr. The first passivation layer 27 protects the underlying first III-V compound layer 23 from damage in the following processes having plasma.

Referring to FIG. 2B, two openings 27 o are formed from the top surface of the first passivation layer 27 to a portion of the first III-V compound layer 23. Two openings 27 o in the first passivation layer 27 are defined by lithography and etching processes to expose a portion of the first III-V compound layer 23. The opening 27 o is stair shape. In some embodiments, the stair is around the middle portion of the sidewall of the first passivation layer 27, and thus the height h3 of the upper portion of the stepped-shape openings 27 o is less than the height h4 of the lower portion of the stepped-shape openings 27 o. In some embodiments, the width w2 of the step is in a range from about 0.03 μm to about 0.05 μm.

Referring to FIG. 2C, a metal layer 241 is deposited over the first passivation layer 27, filling into the openings of the first passivation layer 27 and contacting the first III-V compound layer 23. In some embodiments, the metal layer 241 is deposited by using sputtering, atomic layer deposition (ALD) or physical vapor deposition (PVD) operations. In some embodiments, the metal layer 241 includes Au, Al, Ti, Ni, Au or Cu. The metal layer 241 has two openings 2410 located over the openings 27 o shown in FIG. 2B.

Referring to FIG. 2D, a photoresist (or mask) 241 m is placed on the metal layer 241 and filling into the openings 2410 of the metal layer 241. The photoresist 241 m is patterned to serve as an etching mask.

Referring to FIG. 2E, an etching back operation is performed on the photoresist 241 m to remove the photoresist from the top surface of the metal layer 241 and the remaining photoresist 241 m 1 is disposed in the openings of the metal layer 241. As illustrated in FIG. 2E, a top surface of the remaining photoresist 241 m 1 is lower than the top surface of the metal layer 241. However, the top surface of the remaining photoresist 241 m 1 may be substantially at the same height or higher than the top surface of the metal layer 241. The photoresist layer can serve as the etch mask for subsequent operations. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

Referring to FIG. 2F, the metal layer 241 not covered by the photoresist 241 m 1 is removed by an etching operation, such as a reactive ion etch (RIE) process that etches the exposed portions of the metal layer 241, is conducted and the etch until the underlying first passivation layer 27 is exposed. The source region 24 and the drain region 25 can be obtained after the etching operation. The photoresist layer 241 m 1 is removed after the formation of the source region 24 and the drain region 25. During the etching operation, the photoresist 241 m reacts with the recessed sidewall of the metal layer 241 and form byproducts that are resistant to the RIE. The byproduct may be in a form of triangular region (from a cross sectional view) surrounding the recessed sidewall of the metal layer 241. Because the byproduct region is resistant to the RIE, and at the same time, the byproduct region is disposed over the step at the sidewall of the first passivation layer 27, serving as an etching stop-layer to prevent the metal layer from being etched further down to the openings of the first passivation layer 27. The first passivation layer 27 protects the underlying first III-V compound layer 23 from damage during the etching operation.

Note the source region 24 and the drain region 25 are formed by a self-align process where the photoresist 241 m 1 serves as an etching mask defining the shape of the source region 24 and the drain region 25.

Next, a protection layer (not shown) is optionally deposited on the source region 24, the drain region 25 and the first passivation layer 27. In some embodiments, the protection layer includes dielectric materials such as SiO₂ or Si₃N₄. In one example, the protection layer is Si₃N₄. and is formed by performing a plasma enhanced chemical vapor deposition (PECVD) method.

Referring to FIG. 2G, a second passivation layer 28 is deposited on the source region 24, the drain region 25 and the first passivation layer 27. In some embodiments, the second passivation layer 28 is in a thickness range from about 3 nm to about 20 nm. In some examples, the second passivation layer 28 comprises silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide or hafnium oxide. In one embodiment, the second passivation layer 28 is formed by an atomic layer deposition (ALD) method. The ALD method is based on the sequential use of a gas phase chemical process. The majority of ALD reactions use two chemicals, typically called precursors. These precursors react with a surface one-at-a-time in a sequential manner. By exposing the precursors to the growth surface repeatedly, the second passivation layer 28 is deposited. The ALD method provides a uniform thickness of the second passivation layer 28 with high quality. In one example, the second passivation layer 28 is zirconium oxide. In some embodiments, a first precursor includes tetrakis[ethylmethylamino]zirconium (TEMAZr) or zirconium chloride (ZrCl₄). In some embodiments, a second precursor includes oxygen in order to oxidize the first precursor material to form a monolayer. In some examples, the second precursor includes ozone (O₃), oxygen, water (H₂O), N₂O or H₂O₂. In other embodiments, the second passivation layer 28 is formed by a plasma enhanced chemical vapor deposition (PECVD) or a low pressure chemical vapor deposition (LPCVD).

Referring to FIG. 2H, an opening is formed in the second passivation layer 28 and the first passivation layer 27. The opening is disposed between the source region 24 and the drain region 25 to expose a top surface of the first III-V compound layer 23. Then a metal layer is deposited in the opening to from the gate region 26. In some embodiments, the gate region 26 includes a refractory metal or its compounds, e.g., titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW) and tungsten (W). Alternatively, the gate region 26 includes nickel (Ni), gold (Au) or copper (Cu).

As stated above, reducing the overlaying width of the source region and the first passivation layer as well as the overlaying width of the drain region and the first passivation layer would reduce the on resistance of the semiconductor structure. As shown in FIG. 2F, during the etching operation, the photoresist 241 m reacts with the recessed sidewall of the metal layer 241 and form byproducts that are resistant to the RIE. The byproduct may be in a form of triangular region (from a cross sectional view) surrounding the recessed sidewall of the metal layer 241. Because the byproduct region is resistant to the RIE, and at the same time, the byproduct region is disposed over the step at the sidewall of the first passivation layer 27, serving as an etching stop-layer to prevent the metal layer from being etched further down to the openings of the first passivation layer 27. The first passivation layer 27 protects the underlying first III-V compound layer 23 from damage during the etching operation. Therefore, no further photoresist is required for metal layer etching to form the source region 24 and the drain region 25. Therefore, in comparison with the existing approaches that use a further photoresist for metal etching to form the source region or drain region, the operations shown in FIGS. 2A-2H would reduce the manufacturing cost.

In addition, as shown in FIG. 2B, the overlaying width of the source/drain region and the first passivation layer is defined by the width w2 of the stepped-shape sidewall of the first passivation layer 27. In comparison with the existing semiconductor structure (in which the overlaying width is about 0.2 μm), the semiconductor structure formed by the operations shown in FIGS. 2A-2H has smaller overlaying width (in a range from about 0.03 μm to about 0.05 μm). Reducing the overlaying width would reduce the on resistance of the semiconductor device, which would in turn enhance the performance of the semiconductor device.

FIG. 3A to FIG. 3F are cross-sectional views of a CMOS-MEMS structure fabricated at various stages, in accordance with some embodiments of the present disclosure. The manufacturing steps shown in FIG. 3A to FIG. 3F are similar to those in FIG. 2C to FIG. 2H except that in FIG. 3A, a hard mask 31 is further deposited on the metal layer 241 by a CVD operation. In some embodiments, the hard mask 31 is lining over the sidewall and heating element bottom of the opening 2410 of the metal layer 241. Subsequently, a portion of the hard mask 31 not in the opening 2410 is being removed. Referring to FIG. 3D, a portion of the hard mask 31 would be removed and only parts of the source region 24 and the drain region 25 are covered by the hard mask 31. In some embodiments, the hard mask 31 includes nitrides or oxide. In some embodiments, the thickness of the hard mask 31 is in a range from about 50 Å to 500 Å.

In view of the above, the present disclosure provides a semiconductor structure with smaller on resistance by reducing the overlaying width of the source/drain region and the passivation layer. In addition, the present disclosure provides a method for manufacturing the semiconductor structure by using self-aligned operation without using an extra photoresist or hard mask to form the source/drain region.

One embodiment of the present disclosure provides a semiconductor device. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a first passivation layer on the first III-V compound layer, a source region and a drain region. The source region penetrates the first passivation layer to electrically contact the first III-V compound layer. The drain region penetrates the first passivation layer to electrically contact the first III-V compound layer. A sidewall of the first passivation layer contacting with the source region comprises a stair shape.

One embodiment of the present disclosure provides a high electron mobility transistor (HEMT). The HEMT comprises a substrate, a first III-V compound layer over the substrate, a first passivation layer on the first III-V compound layer, a source region and a drain region. The source region penetrates the first passivation layer to electrically contact the first III-V compound layer. The drain region penetrates the first passivation layer to electrically contact the first III-V compound layer. An upper portion of the source region overlays the first passivation layer, and a width of the upper portion overlaying the first passivation layer is in a range from approximately 0.03 μm to approximately 0.05 μm.

One embodiment of the present disclosure provides a method of manufacturing a semiconductor device, comprising: providing a substrate, forming a first III-V compound layer over the substrate, forming a first passivation layer over the first III-V compound layer, forming a first opening from a top surface of the first passivation layer to the first III-V compound layer, each opening having a stair-shaped sidewall at the first passivation layer, depositing a metal layer over the first passivation layer and in the first opening, the metal layer having a second opening above the corresponding first opening, and removing a portion of the metal layer to form a source region and a drain region.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As those skilled in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, composition of matter, means, methods or steps presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such as processes, machines, manufacture, compositions of matter, means, methods or steps/operations. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure. 

What is claimed is:
 1. A method for manufacturing a semiconductor device, comprising: providing a substrate; forming a first III-V compound layer over the substrate; forming a first passivation layer over the first III-V compound layer; forming a plurality of first openings from a top surface of the first passivation layer to the first III-V compound layer; depositing a metal layer over the first passivation layer and in the plurality of first openings, the metal layer having a plurality of second openings above and corresponding to each of the plurality of first openings; forming a hard mask conforming to the metal layer; placing a photoresist over the hard mask and in the plurality of second openings; and removing a portion of the metal layer to form a source electrode and a drain electrode.
 2. The method of claim 1, wherein forming the source electrode and the drain electrode further comprises removing a portion of the photoresist until the remaining photoresist being in the plurality of second openings.
 3. The method of claim 2, wherein a portion of an inner sidewall of the hard mask is exposed from the photoresist subsequent to removing the portion of the photoresist.
 4. The method of claim 1, further comprising removing a portion of the hard mask until the remaining hard mask being in the plurality of second openings.
 5. The method of claim 4, wherein forming the source electrode and the drain electrode comprises etching a portion of the metal layer free from a coverage of the remaining hard mask.
 6. The method of claim 5, further comprising forming a second passivation layer over the remaining hard mask and the first passivation layer subsequent to removing the portion of the metal layer.
 7. The method of claim 6, further comprising forming an opening in the second passivation layer and the first passivation layer between the source electrode and the drain electrode.
 8. The method of claim 1, wherein an upper portion of each of the second openings has a width greater than a width of a bottom portion of each of the second openings.
 9. The method of claim 1, wherein each of the plurality of first openings has an upper portion wider than a lower portion.
 10. A method for manufacturing a semiconductor device, comprising: providing a substrate; forming a first III-V compound layer over the substrate; forming a first opening from a top surface of the first III-V compound layer; depositing a metal layer in the first opening, the metal layer having a second opening above and corresponding to the first opening; removing a portion of the metal layer to form a source electrode; and forming a hard mask lining the second opening of the metal layer.
 11. The method of claim 10, further comprising forming a passivation layer over the source electrode.
 12. The method of claim 11, further comprising forming a second opening in the passivation layer and adjacent to the source electrode.
 13. A semiconductor device, comprising: a substrate; a first III-V compound layer over the substrate; a first passivation layer on the first III-V compound layer; a source electrode penetrating the first passivation layer to electrically contact the first III-V compound layer; a drain electrode penetrating the first passivation layer to electrically contact the first III-V compound layer, wherein a lower portion of the source electrode is directly surrounded by the first passivation layer, the lower portion comprising: an upper part having a first width; and a lower part having a second width, the first width being greater than the second width; and a first hard mask lining a bottom and a sidewall of the drain electrode.
 14. The semiconductor device of claim 13, further comprising a second hard mask lining a bottom and a sidewall of the source electrode.
 15. The semiconductor device of claim 14, further comprising a second passivation layer over the first hard mask, the second hard mask, the source electrode, and the drain electrode.
 16. The semiconductor device of claim 15, wherein the second passivation layer is in direct contact with a portion of the first passivation layer free from a coverage of a vertical projection of the first hard mask and the second hard mask.
 17. The semiconductor device of claim 14, wherein a thickness of the first hard mask is in a range from 50 Angstrom to 500 Angstrom.
 18. The semiconductor device of claim 14, wherein the first III-V compound layer comprises AlGaAs or AlInP.
 19. The semiconductor device of claim 14, further comprising a second III-V compound layer between the first III-V compound layer and the substrate.
 20. The semiconductor device of claim 14, further comprising a gate electrode penetrating the first passivation layer and the second passivation layer. 